Conventionally, a bit synchronization circuit and the like, which correspond to various user's use conditions, are provided in a custom IC such as an application specific integrated circuit (ASIC).
This bit synchronization circuit is a circuit for latching input data that are input asynchronously using a half cycle delayed clock from a data edge, which is output from a multiphase output phase locked loop (PLL) and synchronizing with clocks in a receiving side.
Further, error avoidance technique for latching data of the bit synchronization circuit has been known, which decides a clock having level transition timing in a central portion of level transition timing from data being adjacent alternately and identified by a phase clock which is different by majority decision with time series of a phase detect output (for example, refer to the patent document 1).
Further, as reducing technique of the jitters of delay locked loop (DLL), phase matching technique between a delay clock and a standard clock has been known by adjusting delay time based on plural phase comparison results between the standard clock and the delayed clock of a phase detect circuit by deciding the majority of phase comparison results (for example, refer to the patent document 2).
[Patent document 1] JP-A No. 186111/2001
[Patent document 2] U.S. Pat. No. 2001/28266A1
However, the following problems are found by the inventor in data latching technique of the foregoing bit synchronization circuit:
FIG. 26 is a block diagram of a bit synchronization circuit 50 which has been examined by the inventor.
The bit synchronization circuit 50 includes, for example, a flip-flop 51, a phase detect circuit 52, a pointer 53, a selector 54, and a multiphase clock output PLL 55.
The flip-flop 51 latches input data. The phase detect circuit 52 compares phases between input data and a clock phase having a half cycle forward to a clock of latching the foregoing data, and an UP (up) or DN (down) signal is output based on its comparison result.
The pointer 53 controls the selector 54 by receiving the UP or DOWN signal. The selector 54 changes and supplies a clock phase that is output from the multiphase clock output PLL 55 to the flip-flop 51, based on the control of the pointer 53.
In the bit synchronization circuit 50 for selecting such a clock phase, latency up to the time that the clock phase supplied to the flip-flop 51 changes by operating the pointer 53 and the selector 54 based on the results of phase comparison becomes large after comparing phases.
Thus, if the UP or DOWN signal is output to a pointer every time that a phase detect circuit compares the phases, as indicated in FIG. 27, in the event that the jitters are caused severely in the input data, data latching clock also changes by following the foregoing jitters after delay time.
Thus, a problem arises, in which data are acquired by a delay clock phase different from a clock phase for a period of the foregoing delay time, even if a data edge returns to an original position, and the error rate of latching data becomes large in the worst case since data cannot be read correctly.
Further, in the bit synchronization circuit as set forth in the patent document 1, a synchronous error, such as the jitters and SNR degradation, is prevented by deciding the three bit majority of the result of the phase detect circuit 3 in a time-series way. Although the synchronous error can be prevented from comparatively fast changing noises within input cycle time, such as the jitters because phase matching between the data and the clock is performed at the time of inputting BSEN, the situation of containing fluctuation, a so-called wander, caused more slowly than cycle time of the input data in the input data has not been considered. Thus, the inventor noticed that a latching error might be caused in the worst case.
Further, in a delay control circuit 34 using the majority circuit as mentioned in FIG. 4 of the patent document 2, three values such as a forward signal FW, a backward signal BW, and a coincidence signal LON are input from a phase detect circuit 20, and phase matching is made by deciding its majority. Because three values are input from the phase detect circuit 20, each corresponding counter must however be provided. Thus, the inventor noticed that circuit diagram size and power dissipation became large.
Further, during phase matching using the majority decision circuit, if the number of majority decision counts of the majority decision circuit is small, then operation time from starting synchronization to actual synchronization becomes short, but the tolerance of the jitters becomes low. On the other hand, the inventor noticed that operation time from starting synchronization to actual synchronization became long although the tolerance of the jitters became high if the number of majority decision counts was large.